1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor substrate, and more particularly to a method of manufacturing a semiconductor substrate suitable for the formation of an electronic device or an integrated circuit provided on a layer of a single crystal semiconductor formed on a dielectric isolation layer or an insulator or provided on a single crystal compound semiconductor formed on an Si substrate.
2. Related Background Art
The formation of a single crystal Si semiconductor layer on an insulator is widely known as a Semiconductor On Insulator (SOI) technique, and much research has been conducted regarding the SOI technique because a device employing the SOI technique provides various advantages that cannot be attained by a bulk Si substrate from which a normal Si integrated circuit is fabricated. That is, the use of the SOI technique provides, for example, the following advantages:
1. Dielectric isolation is facilitated, and high integration is enabled. PA1 2. Excellent radiation resistance is achieved. PA1 3. Stray capacity is reduced to enable high-speed operation. PA1 4. Well processing can be omitted. PA1 5. Latch-up can be prevented. PA1 6. A fully depleted field effect transistor is enabled by making a film thin. They are disclosed in more detail, for example, in Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, Vol. 63, No. 3, 429-590 (1983). PA1 1. Thinning by polishing; PA1 2. Thinning by local plasma etching; and PA1 3. Thinning by selective etching. PA1 The selective ratio of etching is insufficient such that it is about 10.sup.2 at the maximum. PA1 Because the surface property after being etched is poor, touch polishing is required after the etching. However, as a result, the film thickness is reduced, and the uniformity of the film thickness is liable to be deteriorated. In particular, the amount of polishing is managed by time, but because the fluctuation of a polishing rate is large, it is difficult to control the amount of polishing. Therefore, this problem becomes severe particularly when a very-thin SOI layer such as 100 nm is formed. PA1 Because ion implantation, epitaxial growth or hetero-epitaxial growth on a high-concentration B doped Si layer is used, the crystallinity of the SOI layer is low. Also, the surface property of the surface to be bonded is inferior to a normal Si wafer. PA1 a sufficient tensile force or pressure is uniformly applied perpendicularly toward the in-plane of the bonded wafers; PA1 a wave energy such as an ultrasonic wave is applied; PA1 the porous layer is allowed to appear on the wafer edge surface, the porous Si is etched to some degree, and a member sharp as a razor blade is inserted into the etched porous Si; PA1 the porous layer is allowed to appear on the wafer edge surface, and after a liquid such as water is permitted to permeate the porous Si, the entire bonded wafers are heated or cooled to inflate the liquid; or PA1 a force is exerted on the first (or second) substrate horizontally to the second (or first) substrate. PA1 preparing a first substrate having a porous region including at least two layers different in porosity and a non-porous layer formed on the porous region; PA1 bonding a surface of the non-porous layer of the first substrate to a surface of a second substrate; PA1 separating the first and second substrates from each other to transfer the non-porous layer to the second substrate; and PA1 removing the residual portion of the porous region remaining on a separation surface of the second substrate or making the residual portion non-porous to smooth the separation surface; PA1 wherein the step for preparing the first substrate comprises a step of forming a first porous layer of 1 .mu.m or less in thickness, a second porous layer adjacent to the first porous layer and high in porosity, and the non-porous layer adjacent to the first porous layer.
Further, in recent years, it has been frequently reported that an SOI substrate is a substrate that realizes an increase in operation speed of a MOSFET and a reduction in power consumption thereof (IEEE SOI conference 1994). Also, the use of the SOI structure simplifies the element isolation process more than where an element is formed on the bulk Si wafer. This is because an insulating layer is formed on a lower portion of the element, and, as a result, a device processing process is shortened. In other words, it is expected that the wafer costs and the process costs are reduced in total in comparison with the MOSFET or IC formed on the bulk Si, while achieving high performance characteristics.
In particular, the fully depleted MOSFET is expected to increase operation speed and to reduce power consumption due to an improvement of driving force. A threshold voltage (Vth) of the MOSFET is generally determined according to the density of impurities in a channel section, but in a fully depleted MOSFET using the SOI, a thickness of the depletion layer is affected by a thickness of the SOI. Therefore, in order to manufacture a large-scaled integrated circuit with an excellent yield, a great demand has arisen for the thickness of the SOI film to be uniform.
Also, the devices on a compound semiconductor have high performance which cannot be obtained by Si, for example, features such as a high-speed operation or light emission. At the present, those devices are almost formed in an epitaxially grown layer formed on a compound semiconductor substrate made of GaAs. However, the compound semiconductor substrate suffers from such problems that the substrate is expensive and low in mechanical strength and that manufacturing of a large-area wafer is difficult.
From the above viewpoints, an attempt has been made to allow a compound semiconductor to epitaxially grow on the Si wafer which is inexpensive and high in mechanical strength and from which a large-area wafer can be manufactured.
Research in the formation of the SOI substrate has been extensively conducted since the 1970's. Initially, a method in which single crystal Si is allowed to hetero-epitaxially grow on a sapphire substrate which is an insulator (SOS: Sapphire on Silicon), a method of forming an SOI structure through dielectric isolation by porous oxidized Si (FIPOS: Fully Isolation by Porous Oxidized Silicon), and an oxygen ion implantation method have been extensively studied.
The FIPOS method is a method in which an N-type Si layer is formed on a surface of a P-type Si single crystal substrate in the form of an island by implanting proton ions (Imai et al., J. Crystal Growth, Vol. 63, 547(1983)) or by epitaxial growth and patterning. Only a P-type Si substrate is made porous through an anodization method in an HF solution so as to surround the Si island from the surface. Thereafter the N-type Si island is dielectrically isolated by accelerating oxidation. The degree of device design freedom may be restricted because the Si region isolated is determined prior to device processing.
The oxygen ion implantation method is directed to a method which is called "SIMOX" initially reported by K. Izumi. In the method, after oxygen ions of about 10.sup.17 to 10.sup.18 /cm.sup.2 are implanted into a Si wafer, the Si wafer is annealed at a high temperature of about 1,320.degree. C. in an argon/oxygen atmosphere. As a result, implanted oxygen ions mainly having a depth corresponding to a projection range (Rp) of ion implantation are bonded to Si to form a Si oxide layer. At this time, the Si layer which is made amorphous by implantation of oxygen ions on an upper portion of the Si oxide layer is also recrystallized to form a single crystal Si layer. Although the number of defects contained in the Si layer of the surface is conventionally large, that is, 10.sup.5 /cm.sup.2, it has been successfully reduced to about 10.sup.2 /cm.sup.2 by setting the amount of implanted oxygen to about 4.times.10.sup.17 /cm.sup.2. However, because the ranges of the implantation energy and the amount of implantation by which the quality of the Si oxide film, the crystallinity of the surface Si layer, etc. can be maintained are narrow, the thicknesses of the surface Si layer and the buried oxide Si layer (BOX: Buried Oxide) are limited to specific values. In order to obtain the surface Si layer having a desired thickness, it is necessary to conduct sacrificial oxidation or epitaxial growth. In this case, thickness distribution suffers such that thickness uniformity deteriorates as a result of the superimposition of the deterioration of those processes.
Also, it has been reported that a residual Si region in a silicon oxide which is called "pipe" exists in the BOX. A foreign matter such as dust during implanting has been considered as one cause. On a portion where the pipe exists, the device characteristic is deteriorated by leakage between an active layer and a support member.
Because the ion implantation of the SIMOX is more in the amount of implantation than the ion implantation used in a normal semiconductor process as described above, a period of time when ion is implanted is long even with an exclusive apparatus being developed. Because the ion implantation is conducted by raster-scanning an ion beam having a predetermined current amount or expanding an ion beam, it is presumed that the implantation period increases with an increased area of the wafer. Also, it has been pointed out that a high-temperature heat treatment on the large-area wafer causes a more sever slip problem due to the distribution of the temperature within the wafer more. In the SIMOX, since it is essential to conduct a heat treatment at a high temperature which is not normally used in the Si semiconductor process, such as 1300.degree. C. or higher, there is a fear that the problems to be overcome such as the device development, metal contamination or slip become more pronounced.
Also, apart from the above-described conventional SOI forming method, in the recent years, attention has been paid to a method in which a Si single crystal substrate is bonded to another Si single crystal substrate thermally oxidized with a heat treatment or an adhesive to form an SOI structure. This method requires a process of making an active layer uniformly thin for a device. In other words, Si single crystal substrate several hundreds .mu.m in thickness is required to be made thin on the order of .mu.m or less. The thinning process is made by three kinds of methods stated below.
In the method 1, it is difficult to uniformly thin the substrate. In particular, thinning of sub .mu.m causes the fluctuation of several tens %, and this thinning suffers from a severe problem. Also, as the diameter of the wafer is increased, difficulty is increased.
In the method 2, after the substrate is made thin by polishing in the method 1 up to about 1 to 3 .mu.m in advance, the distribution of the film thickness is measured over the entire surface at multi-points, and plasma using SF.sub.6 of several mm in diameter is scanned on the basis of the measured distribution of the film thickness so that etching is conducted while the distribution of the film thickness is being corrected, thereby thinning the substrate to a desired thickness. It has been reported that this method enables the distribution of the film thickness to be adjusted to about .+-.10 nm. However, if a particle exists on the substrate at the time of plasma etching, because the particle functions as an etching mask, a projection is formed on the substrate.
Because the surface of the substrate is rough immediately after the substrate is plasma-etched, touch polishing is required after the plasma etching has been completed. However, since the amount of polishing is time-controlled, the control of final film thickness and the deterioration of the distribution of the thickness by polishing has been noted. Also, in a polishing process, since an abrasive powder such as colloidal silica directly polishes the surface that will form an active layer, there are fears that a damaged layer is formed by polishing and that machining distortion is introduced. Further, in the case where the area of the wafer is enlarged, there is a fear that through-put is remarkably reduced because the plasma etching period increases in proportion to an increase of the wafer area.
The method 3 is directed to a method in which a film structure which can be selectively etched is made on the substrate to be made thin in advance. For example, a P.sup.+ Si thin layer and a P-type Si thin layer each containing boron of 10.sup.19 /cm.sup.3 or more are superposed onto a P-type substrate through a method such as epitaxial growth to form a first substrate. After this substrate is bonded to a second substrate through an insulating layer such as an oxide film, a back surface of the first substrate is thinned by grinding or polishing in advance. Thereafter, the P-type layer is selectively etched to expose the P.sup.+ layer, and also the P.sup.+ layer is selectively etched to expose the P-type layer, thus completing the SOI structure. This method is disclosed in more detail by the report of Maszara (W. P. Maszara, J. Electrochem. Soc., Vol. 138, 341(1991)).
It is said that the selective etching is effective in a uniform thin film formation, but the selective etching suffers from the following problems.
The above description is reported by C. Harendt, et al., J. Elect. Mater. Vol. 20, 267 (1991), H. Baumgart, et al., Proceeding of the 1st International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, (The Electrochemical Society) Vol. 92-7, 375, and C. E. Hunt, et al., Proceeding of the 1st International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, (The Electrochemical Society) Vol. 92-7, 165.
Also, the selectivity of the selective etching largely depends on a difference in concentration of impurities such as boron and the abruptness of the profile in its depth direction. Therefore, if bonding annealing at a high temperature for enhancing a bonding strength or epitaxial growth at a high temperature for improving crystallinity is conducted, the distribution of impurity concentration in the depth direction is expanded to thereby deteriorate the selectivity of etching. In other words, it is difficult to improve all of the selective ratio of the etching, the crystallinity and bonding strength together.
In the recent years, Yonehara, et al. have reported a bonding SOI which solves the above problems, is excellent in the uniformity of the film thickness and crystallinity, and can be batch-processed (T. Yonehara, et al., Appl. Phys. Letter Vol. 64, 2108 (1994)). This method employs a porous layer 32 of an Si substrate 31 as a material of selective etching. After a non-porous single crystal Si layer 33 is allowed to epitaxially grow on the porous layer, it is bonded to a second substrate 34 through a Si oxide layer (insulating film) 35 (FIG. 5A). A first substrate is made thin from its back surface through a grinding method or the like so that the porous Si is exposed over the entire surface of the substrate (FIG. 5B). The exposed porous Si is etched with a selective etchant such as KOH or HF+H.sub.2 O.sub.2 so as to be removed (FIG. 5C). At this time, since the etching selective ratio of the porous Si to the bulk Si (non-porous single crystal Si) can be made as high as 100,000, the non-porous single crystal Si layer that has grown on the porous Si in advance remains on the second substrate without substantially reducing its thickness, thereby making possible the formation of an SOI substrate. Therefore, uniformity of the thickness of the SOI is determined substantially during epitaxial growth. Since a CVD device used in a normal semiconductor process can be employed for epitaxial growth, according to the report (SSDM95) by Sato, et al., it is realized that its uniformity is, for example, within 100 nm.+-.2%. Also, it is reported that the crystallinity of the epitaxial Si layer is also excellent and 3.5.times.10.sup.2 /cm.sup.2.
The porous Si has been discovered by Uhlir, et al., during study of electrolytic polishing of semiconductor (A. Uhlir, Bell Syst. Tech. J., Vol. 35 333(1956)). The porous Si can be formed by subjecting a Si substrate to anodization in an HF solution. The porous Si has micro-pores like sponge formed by electrolyte etching in bulk Si, and has pores about several nm in diameter, for example, with a density of about 10.sup.11 /cm.sup.2, depending on the conditions of anodization and the specific resistance of Si.
Unagami, et al., have studied dissolution reaction of Si in anodization and reported that positive holes are required for anodic reaction of Si in an HF solution, and its reaction is made as follows (T. Unagami, J. Elecrochem. Soc., Vol. 127, 476 (1980)). EQU Si+2HF+(2-n)e.sup.+ .fwdarw.SiF.sub.2 +2H.sup.+ +ne.sup.- EQU SiF.sub.2 +2HF.fwdarw.SiF.sub.4 +H.sub.2 EQU SiF.sub.4 +2HF.fwdarw.H.sub.2 SiF.sub.6
or EQU Si+4HF+(4-.lambda.)e.sup.+ .fwdarw.SiF.sub.4 +4H.sup.+ +.lambda.e.sup.- EQU SiF.sub.4 +2HF.fwdarw.H.sub.2 SiF.sub.6
where e.sup.+ and e.sup.- represent a positive hole and an electron, respectively. Also, n and .lambda. represent the number of positive holes necessary for dissolving Si of one atom, respectively, and in the case where a condition of n&gt;2 or .lambda.&gt;4 is satisfied, the porous Si is formed.
From the above viewpoints, the P-type Si where positive holes exist is made porous, but the N-type Si is not made porous. The selectivity at the time of porous structure formation has been proved by Nagano, et al., and Imai (Nagano, Nakajima, Yasuno, Onaka, Kajiwara, Electronic communication society technical research report, Vol.79, SSD79-9549(1979) and (K. Imai, Solid-state Electronics, Vol.24, 159(1981)).
In the conventional method, because the selectivity of etching is determined by a difference in impurity concentration and a profile in its depth direction, a heat treatment temperature which causes the distribution of concentration to be expanded (bonding, epitaxial growth, oxidization, etc.) is largely limited to about 800.degree. C. or below. On the other hand, in the etching of this method, it has been reported that because an etching rate is determined according to a structural difference between the porous structure and the bulk, the limitation of the heat treatment temperature is small to such an extent that the heat treatment at about 1,180.degree. C. is enabled. For example, there has been known that a heat treatment after bonding wafers to each other enhances an adhesive strength between the wafers and reduces the number and size of voids occurring on the bonding interface. Also, in the etching on the basis of a structural difference, even if a particle stuck onto the porous Si exists, the particle does not adversely affect the uniformity of the film thickness.
Also, in general, a thin film Si layer deposited on a light transmitting substrate represented by glass becomes an amorphous layer or a polycrystal layer at the best because the disorder of the crystal structure of the substrate is reflected, thereby disenabling the manufacture of a high-performance device. This is because the crystal structure of the substrate is amorphous, and even if a Si layer is merely deposited on the substrate, a high-quality single crystal layer cannot be obtained.
However, the semiconductor substrate using bonded wafers always requires two wafers, and a large portion of one of those wafers is uselessly removed by polishing, etching, etc., and abandoned, which causes not only the costs to increase, but also the finite resource in the earth to be wasted.
In order to utilize the features of the SOI using the bonded wafers, a method has been desired in which an SOI substrate having a satisfactory quality is manufactured with a high reproducibility, resources are saved by reusing the wafers, etc., and cost reduction is realized.
A method of reusing a first substrate which is wasted in the bonding method has recently been reported by Sakaguchi, et al. (Japanese Patent Application Laid-Open No. 7-302889).
They have applied the following method instead of a process in which the first substrate is ground from the back surface thereof, and a porous Si is exposed by thinning the first substrate by etching or the like in the method of bonding and conducting etch-back using the above-described porous Si.
After a surface layer of a first Si substrate 41 is made porous to form a porous layer 42, a single crystal Si layer 43 is formed thereon, and the single crystal Si layer 43 is bonded to a main surface of a second Si substrate 44 different from the first Si substrate 41 through an insulating layer 45 (FIG. 6A). Thereafter, the bonded wafers are divided at the porous layer (FIG. 6B), and the porous Si layer exposed from the surface of the second Si substrate is removed by selective etching, thereby forming an SOI substrate (FIG. 6C). The bonded wafers are split within the porous Si layer through one of the following techniques:
Those techniques are based on the consideration that the porous Si is sufficiently weaker than the bulk Si although the mechanical strength of the porous Si, depends on the porosity. For example, it can be presumed that if the porosity degree is 50%, the mechanical strength of the porous Si is half that of the bulk. In other words, if a compressive force, a tensile force or a shearing force is applied to the bonded wafers, the porous Si layer is first destroyed. Also, as the porosity is increased, the porous layer can be destroyed with a weaker force.
In this specification, porosity is defined as a ratio of the volume of total pores to the material of the porous layer in the volume of the porous layer.
However, in a method disclosed in Japanese Patent Application Laid-Open No. 7-302889, a position of the separation in the porous layer in the thickness direction cannot be defined, and a location where separation occurs in the layer is different for each of the wafers, thereby lowering the yield. Furthermore, a thickness of the remaining portions of the porous Si layer after being separated in the wafer surface is dispersed, and even if a high selective etching is employed, the yield may be lowered in order to satisfy the specification of the SOI for high uniformity of the film thickness.
Also, Japanese Patent Application Laid-Open No. 8-213645 discloses a method of separating the bonded wafers at the porous layer, but does not disclose the layer-like structure of the porous layer. Apart from this publication, Proceedings of Applied Physics Society, autumn of 1996, p. 673 by Tayanaka discloses that a current is varied during a process to manufacture a porous Si.
Japanese Patent Application Laid-Open No. 8-213645 discloses that the separation is made from any position in the separation layer, in other words, that a position where separation is made cannot be defined. In this case, the thickness of the remaining porous Si layer within the wafer surface is dispersed, and even if the porous Si is removed by etching, if the rate of etching to the active layer (device layer) which is a non-porous single crystal layer is not 0 (zero), the active layer is somewhat etched to cause the fluctuation of the in-plane of the thickness. Alternatively, even if the substrate is used in a state where the remaining porous Si layer exists, a surface step depending on the separation position remains. Also, even in the above method described in the Proceedings of Applied Physics Society, autumn of 1996, p. 673 by Tayanaka, the separation occurs in the center of the porous Si with the result that the portions of the porous Si layers remaining on both of the substrates must be removed.
It has been considered that the process of etching the porous layer remaining on the surface of the layer transferred onto the second substrate is essential in order to manufacture a high-quality bonded SOI substrate. However, a period required for the etching process is elongated more as the thickness of the remaining porous layer is thick, and also processes such as carrying in/out the substrates to the etching apparatus, management of the etching apparatus or etchant, or cleaning after etching, which are accompanied with the etching process, are required. Therefore, if the etching process can be omitted, a period of time required for manufacturing the SOI substrate can be greatly reduced. Even if the conventional etching process cannot be fully omitted, if the etching period can be greatly reduced, the period of time required for manufacturing the SOI substrate is shortened, thereby providing the SOI substrate inexpensively.